1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. In particular, the invention relates to a method of manufacturing a semiconductor device having a trench gate structure.
2. Description of Related Art
In recent years, attentions have been paid to a device with a gate electrode embedded in a trench, a so-called semiconductor device having a trench gate structure along with improvements in degree of integration of the semiconductor device.
Referring to FIGS. 3A to 3D and FIGS. 4E to 4G, an example of a method of manufacturing a semiconductor device having a trench gate structure is described.
FIGS. 3A to 3D and FIGS. 4E to 4G are longitudinal sectional views schematically illustrating a method of forming a trench gate structure in a manufacturing process of a semiconductor device of the related art.
First, as shown in FIG. 3A, a silicon oxide film 52a is formed on a semiconductor substrate 51 made of single crystal silicon.
Next, as shown in FIG. 3B, an opening 53 of a predetermined pattern is formed in the silicon oxide film 52a by photolithography and etching to thereby form a mask 52 made of silicon oxide.
Next, as shown in FIG. 3C, the mask 52 is used as etching mask upon anisotropic etching to form a trench 54 in the semiconductor substrate 51.
After that, as shown in FIG. 3D, the mask is removed.
Next, as shown in FIG. 4E, a gate insulating film 55 made of silicon oxide with a thickness of about 500 Å is formed on the semiconductor substrate 51 inclusive of a surface of an inner wall of the trench 54 by thermal oxidation.
Next, as shown in FIG. 4F, a conductive film 56 for forming a gate electrode, which is made of polycrystalline silicon is formed on semiconductor substrate 51 by CVD. As a result, the trench 54 is filled with the conductive film 56.
After that, as shown in FIG. 4G, the conductive film 56 for forming a gate electrode is etched back by dry etching to thereby form a gate electrode 57. One of a similar technique is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2001-326273.
However, the above manufacturing method of the related art requires over-etching to complete remove the conductive film 56 from the surface of the gate insulating film 55 at the time of etching back the conductive film 56 to form the gate electrode 57.
Then, upon the over-etching, the gate insulating film 55 functions as an etching stopper, so etching is stopped on the surface of the gate insulating film 55 and etching proceeds on the conductive film 56 in the trench 54.
Therefore, it is inevitable that an upper surface of the gate electrode 57 is positioned below the surface of the semiconductor substrate 51 by a predetermined depth, that is, a difference in level L is formed.
If this difference in level L is formed, there is a possibility that the upper surface of the gate electrode 57 is positioned below the bottom of a source region (not shown) formed in the semiconductor substrate 51 in a subsequent step, and the manufactured device cannot operate as an FET.